The present invention relates to CCD imagers. The present invention particularly relates to CCD technologies, such as virtual phase, wherein one phase is a DC phase.
Higher well capacity in CCD imagers is generally highly desirable, to improve dynamic range. In particular, in virtual phase technology, it is desirable to increase the virtual phase well capacity, if only to permit increases in the capacity of the clocked well too. This could be accomplished by patterning the virtual phase well with larger dimensions, but of course this would be undesirable. Naturally, the ability to provide larger capacitance for the same dimensions also means that dimensions may be made smaller for the same capacitance.
The present invention teaches that higher well capacity, in the DC phase region of any CCD technology (such as virtual phase) which uses a DC phase, can be achieved by using a deep p-type implant to produce a p+ region (or, more precisely, a p-type region having a substantially higher concentration than the p-type substrate background level) underneath the n-type channel region (which itself is underneath the shallow p+ virtual phase electrode, in virtual phase technology).
The present invention also teaches that higher well capacity in the diffused-gate-phase region of any CCD technology which uses both diffused-gate-phase regions and patterned-gate-phase regions can be achieved by using a deep blanket p-type implant to produce a p+ region (or, more precisely, a p-type region having a substantially higher concentration than the p-type substrate background level) underneath the n-type channel region in the diffused-gate-phase regions.
The depletion width of the interface between channel and substrate can thus be substantially reduced, and the channel to substrate capacitance is accordingly increased. Up to 100% improvement in capacitance is possible using this method. This implies higher well capacity.
A deep p-type implant under an n-type region (referred to as a "Hi-C implant") has long been known in DRAM technology as a way to get more capacitance. However, in CCD technology use of such a deep implant under the channel generally would cause difficulties: the voltage swings required of a clocked electrode over such a Hi-C implant would be increased, contrary to the general efforts to reduce the magnitude of the drive voltages.
Thus, the present invention is particularly advantageous in virtual phase CCD technology; but it is also advantageous in any technology where at least one phase is clocked and at least one other is DC, or in any CCD technology where at least one phase uses an insulated gate electrode (or some other type of patterned electrode) and at least one other phase uses a diffused electrode (or some other type of electrode, such as a self-aligned silicide, which is too thin to stop the channel-stop implants).
The deep P implant is preferably performed after the patterned-gate-phase electrode has been patterned, so that this implant can be unmasked within the CCD array. The patterned-gate-phase electrode (which may be, e.g., of polysilicon, or may be a sandwich structure such as polysilicon/SiO.sub.2 or polysilicon/indium tin oxide) protects the regions under it from the deep implant.
Thus, it is an advantage of the present invention that the capacity of the DC phase well region is increased, with no increase in its dimensions.
It is a further advantage of the present invention that the capacity of the DC phase well region is increased, with no increase in required clock voltage magnitudes of the clocked electrodes.
It is a further advantage of the present invention that the dimensions of the DC phase well region can be reduced without reducing the capacitance of the well.
It is a further advantage of the present invention that the capacity of the DC phase well region is increased, with no increase in required clock voltage magnitudes of the clocked electrodes.
It is a further advantage of the present invention that the capacity of the DC phase well region is increased, without any required increase in the number of patterning steps during fabrication.
It is a further advantage of the present invention that the capacity of the DC phase well region is increased, with no increase in required clock voltage magnitudes of the clocked electrodes nor in dimensions.
The "DC phase" referred to may of course not be entirely DC, since parasitic resistances and capacitances will commonly lead to small voltage swings even in unclocked regions; therefore the references to "DC phase" in this application should be construed more broadly to refer to any phase which is not clocked, regardless of whether it is held at a DC potential or permitted to float to some extent.
According to the present invention there is provided: A CCD device comprising: a substrate having a p-type crystalline semiconductor upper portion containing a plurality of CCD elements connected in series, each said CCD element comprising a clocked phase portion and a DC phase portion, each of said clocked phase portions and each of said DC phase portions including both a well region and a barrier region, at least some of said well regions of said DC phase portions comprising both an n-type channel region and a p-type capacitance-enhancing region thereunder, said p-type capacitance-enhancing region having a higher doping concentration than said semiconductor upper portion.